Panther Lake and Clearwater Woodland in open-source compilers
Intel engineers laying the groundwork for the next-gen CPU sequence.
GCC and LLVM/Clang constitute two broadly followed compilers within the C language circle of relatives. GCC, brief for the GNU Compiler Assortment, contains a number of compilers designed for quite a lot of programming languages equivalent to C, C++, Goal-C, Fortran, Ada, and Pass. As probably the most oldest and maximum prevalent open-source compilers. Alternatively, LLVM/Clang is a more recent compiler undertaking known for its swift and modular structure, in a position to parsing C, C++, and their derivatives.
Each GCC and LLVM/Clang function below open-source ideas, making their supply code out there to the general public for contribution and customization. Intel engineers actively take part in bettering those compilers, making sure compatibility with approaching processor sequence like Panther Lake and Clearwater Woodland.
The patches showed ISA (Instruction Set Structure) for Panther Lake as following:
+Intel Panther Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and PREFETCHI instruction set reinforce.
Each CPU sequence are expected to release in 2025. Sooner than introducing the Panther/Clearwater sequence, Intel plans to unveil different CPU sequence, particularly Arrow Lake, Lunar Lake, and Sierra Woodland, all of which function precursors to the Panther/Clearwater lineup.
Intel has already submitted patches for Meteor, Arrow, and Lunar Lakes, with Panther Lake doubtlessly integrating with GCC model 14, as reported through Phoronix. The GCC compilers practice an annual liberate agenda, indicating that once the upcoming liberate of GCC 14, Intel will prolong reinforce for its 2025 product lineup. Conversely, AMD is predicted to introduce preliminary patches as soon as the brand new sequence begins transport.
RUMORED Intel Shopper CPU Roadmap | ||||||
---|---|---|---|---|---|---|
VideoCardz | Core 13000/14000 | Core (Extremely) 100 | Core (Extremely) 200 | Core (Extremely) 300 | Core (Extremely) 400 | Core (Extremely) 500 |
Raptor Lake (RPL) & Refresh (RPL-R) | Meteor Lake (MTL) | Arrow Lake (ARL) Lunar Lake (LNL) | Arrow Lake Refresh (ARL-R) | Panther Lake (PNL) | Nova Lake (NVL) | |
Release Date | 2022-2023 | This fall 2024 | This fall 2024/H1 2025 | H2 2025 | This fall 2025/H1 2026 | 2026+ |
Node | Intel 7 | Intel 4 | TSMC N3B/Intel 20A | TSMC N3B/Intel 20A | Intel 18A | TSMC N2P/Intel 16/14A |
Large Core µArch | Raptor Cove | Redwood Cove | Lion Cove | Lion Cove | Cougar Cove | TBC |
Small Core µArch | Gracemont | Crestmont | Skymont | Skymont | Darkmont | Arctic Wolf |
Graphics µArch | Xe-LP | Xe-LPG | Xe-LPG (ARL) Xe²-LPG (LNL) | Xe-LPG | Xe²-LPG | Xe³-LPG |
Max Core Depend | 24 (8P+16E) | 14 (6P+8E+2E) | 24 (8P+16E+2E) (ARL) 8 (4P+4E+2E) (LNL) | 40 (8P+32E+2E) | TBC | 48 (16P+32E+2E) |
Desktop Socket | LGA-1700 | – | LGA-1851 | LGA-1851 | LGA-1851 | TBC |
Reminiscence Beef up | DDR4/DDR5-5600 | DDR5 | DDR5 | DDR5 | DDR5 | TBC |
PCIe Gen | PCIe 5.0 | PCIe 5.0 | PCIe 5.0 | PCIe 5.0 | PCIe 5.0 | TBC |
Supply: Phoronix
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