AMD Future EPYC-E Zen6 leak out
AMD’s next-generation EPYC series for systems on the edge will be powered by Zen6 architecture, reports Moore’s Law is Dead.
The AMD Zen6 architecture is not expected to be available to consumers and data centers anytime soon. The company is yet to release its Zen5 architecture across all market segments, with some Zen4 products still being announced (Hawk Point, MI300 etc.). AMD has a long roadmap, and advanced planning is one of the keys to gaining a foothold in different markets.
The Zen revolution is about to reach its 6th generation with brand-new layout design and new packaging techniques. It will be a major redesign from Zen5, leakers claim. In the EPYC series, AMD is reportedly blending chiplets that incorporate CPU cores, network IP, and custom FPGAs. This approach opens up various new possibilities and gradually blurs the distinctions between traditional CPUs and purpose-specific accelerators.
Around September, MLID shared the first architectural details on Zen5 and Zen6 directly from AMD’s internal slide deck. It confirmed the codename for both architectures as Nirvana and Morpheus. The video mainly focused on Zen5, however the details on Zen6 confirmed that AMD is targeting increased core count per chiplet (up to 32) and supporting high-precision floating point (FP16) operations acceleration for AI and Machine Learning.
AMD EPYC-E with Venice Zen6 cores, Source: Moore’s Law is Dead
MLID has now revealed a diagram featuring EPYC-E product series, where E should stand for Edge. This means telecommunications and edge systems that are designed to use lower core counts and lower power consumption. The product shown in the diagram is Venice SP8 IOD along with two CCDs on each side, featuring 32 Zen6 cores. This special CPU design could also implement NCD (Network Compute Dies) based on Pensando Salina design by replacing some CCDs.
Comparatively, the SP8 socket, which would be used by this EPYC-E design, would be the next CPU socket for some EPYC series. It would launch alongside SP7, which is the socket to host larger Venice CPUs. The SP8 is the smaller socket planned for Siena & Sorano succession.
The EPYC-E would appear in two variants, either a Standard edition with 64 Zen6 cores or 32 cores under “Entry” variant. The Standard edition would have octa-channel DDR5-6400 memory support and 64 PCIe Gen5 plus 32 PCIe Gen6 interface support. The Entry EPYC-C CPUs would have quad-channel memory support of the same speed and 32 (Gen5) and 16 (Gen6) PCIe lanes.
Since one CCD offers 32 cores and the Entry EPYC-E series are locked to such core count, this indicates that AMD could replace one of the CCDs with its NCD tile. Similarly, for the Standard edition, two Zen6 chiplets would be replaced with custom FGPA and NCD dies.
Mockup of AMD EPYC with Zen6 cores for SP7 socket, Source: Moore’s Law is Dead
Access to new documentation and some educated guesses have led MLID into creating a mockup of a possible Zen6 EPYC processor for the SP7 socket. AMD is currently not distinguishing between Zen6 and assumed Zen6c (cloud/dense) cores, which is either because AMD is moving away from this distinction or there are no such cores planned. Regardless, the possible 8 chiplet design with four IOD dies could feature up to 256 Zen6 cores, an increase from current 96 Zen4 (Genoa) or 128 Zen4c (Bergamo) designs, and future Turing with 128/192 Zen5 (classic) or Zen5 (Dense) cores.
Source: Moore’s Law is Dead
